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High speed modified carry save adder using a structure of multiplexers Abstract Adders are the heart of data path circuits for any processor in digital computer and signal processing systems. Growth in technology keeps supporting efficient design of binary adders for high speed applications. In this paper, a fast and area-efficient modified carry save adder (CSA) is presented. A multiplexer based design of full adder is proposed to implement the structure of the CSA. The proposed design of full adder is employed in designing all stages of traditional CSA. By modifying the design of full adder in CSA, the complexity and area of the design can be reduced, resulting in reduced delay time. The VHDL implementations of CSA adders including (the proposed version, traditional CSA, and modified CSAs presented in literature) are simulated using Quartus II synthesis software tool with the altera FPGA EP2C5T144C6 device (Cyclone II). Simulation results of 64-bit adder designs demonstrate the average improvement of 17.75%, 1.60%, and 8.81% respectively for the worst case time, thermal power dissipation and number of FPGA logic elements. Keywords binary adder; carry save adder; high speed; low power; multi operand addition

AbstractThe three-operand binary adder is an essential practical unit to carry out the modular mathematics in numerous cryptography algorithms. The Carry-save adder is mainly used to perform the three-operands addition; however, the propagation delay could be very excessive because of the ripple carry adder present in the carry-save adder. In Han-Carlson adder, the three-operand addition can be accomplished by adding the third operand to the result of the first two operands, but this requires extra hardware. So the area and delays both are simultaneously reduced by the proposed high-speed area-efficient three-operand binary adder. Both the parameters are optimized by replacing the Han-Carlson adder with the Ladner Fischer adder. The proposed architecture is synthesized and implemented with the Xilinx Vivado and Zynq-7000 FPGA family. The Virtual Input-Output (VIO) intellectual prototype concept is used to add three operands, each operand with 32-bit size. The proposed architecture is 1.66 times faster than the Han-Carlson adder with a reduced LUT count. Similar content being viewed by others ReferencesReji SE, Jacob DS (2022) Three—operand binary addition using parallel prefix adders. In: IEEE 19th India council international conference (INDICON). Kochi, India, 2022, pp 1–6. AK, Palisetty R, Ray KC (2020) High-speed area-efficient VLSI architecture of three-operand binary adder. IEEE Trans Circuits Syst I Regul Pap 67(11):3944–3953. MathSciNet Google Scholar Islam MM, Hossain MS, Hasan MK, Shahjalal M, Jang YM (2019) FPGA implementation of high-speed area-efficient processor for elliptic curve point multiplication over prime field. IEEE Access 7:178811–178826Article Google Scholar Liu Z, GroBschadl J, Hu Z, Jarvinen K, Wang H, Verbauwhede I (2017) Elliptic curve cryptography with efficiently computable endomorphisms and its hardware implementations for the Internet of Things. IEEE Trans Comput 66(5):773–785Article MathSciNet Google Scholar Liu Z, Liu D, Zou X (2017) An efficient and flexible hardware implementation of the dual-field elliptic curve cryptographic processor. IEEE Trans Ind Electron 64(3):2353–2362Article Google Scholar Parhami B (2000) Computer arithmetic: algorithms and hardware design. Oxford University Press, New York, NY, USA Google Scholar Download references Author informationAuthors and AffiliationsAnurag University, Hyderabad, Telangana, IndiaGopi Krishna Moodu, G. Srinivasaraju, Amrita Sajja & M. Kiran KumarAuthorsGopi Krishna MooduYou can also search for this author in PubMed Google ScholarG. SrinivasarajuYou can also search for this author in PubMed Google ScholarAmrita SajjaYou can also search for this author in PubMed Google ScholarM. Kiran KumarYou can also search for this author in PubMed Google ScholarCorresponding authorCorrespondence to M. Kiran Kumar . Editor informationEditors and AffiliationsNational Institute of Technology Patna, Patna, Bihar, IndiaPradip Kumar Jain Department of Electrical and Electronics Engineering, Indian Institute of Technology Kanpur, Kanpur, IndiaYatindra Nath Singh Department of Engineering & Technology, University of North Alabama, Florence, SC, USARavi Paul Gollapalli Department of Electronics and Communication Engineering, Mahatma Gandhi Institute of Technology, Gandipet,

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To propagate is less.Why is carry look-ahead adder faster?As because of complex hardware in the circuit, the propagation delays get reduced in the circuit. Here, the device calculates either one/more carries in before the addition, where this minimizes the wait time required to calculate the output of higher bits in the adder.What is a 4 bit look ahead carry adder?A 4-bit carry lookahead adder operates by using 4 full adder circuits. Here, the carry bit is not dependent on any of the carry bits at any stage in the circuit. Only the output is based on the bits that are summed up in the preceding stages and on the carry input bit which is provided at the first stage.So, the circuit at any of the stages has no requirement to wait for the carry-bit generation from the past stages and the carry signal can be known at any timestamp.What is the maximum delay in a 64-bit hierarchical carry look-ahead adder?A 64-bit hierarchical carry-lookahead adder will have a delay of 264 = 128 units of time.What is the critical path delay in a 4-bit CLA?In a CLA, the carry bits are known from carry propagate and carry generate where the whole carry bits are present at the time ‘3’. It also takes one more gate delay to know the sum value. So, all the carry and sum bits are present at time ‘4’. With this, the critical path delay for a 4-bit CLA is 4.What bit of CLA’s can be designed?One can design a carry-lookahead adder with 2-bit, 4-bit, 8-bit, 16-bit and others. It is easy to design2-bit carry-lookahead adder truth table and 2-bit carry-lookahead adder circuit diagram4 bit carry-lookahead adder truth table and 4 bit carry-lookahead adder circuit diagram8 bit carry-lookahead adder truth table and 8 bit carry-lookahead adder circuit diagramHow does a 16-bit CLA is constructed?A 16-bit carry lookahead adder can be designed by using 4 4-bit carry lookahead adders. For this, an additional combinational logic circuit is also needed where it generates carry input for every carry-lookahead adder.How many gates are present in a 16-bit CLA?A 16-bit CLA

W_Cg[1] = i_sum1[1] & i_sum2[1];assign w_Cg[2] = i_sum1[2] & i_sum2[2];assign w_Cg[3] = i_sum1[3] & i_sum2[3];// Creation of carry propogate termsassign w_Cp[0] = i_sum1[0] | i_sum2[0];assign w_Cp[1] = i_sum1[1] | i_sum2[1];assign w_Cp[2] = i_sum1[2] | i_sum2[2];assign w_Cp[3] = i_sum1[3] | i_sum2[3];// Creation of carry termsassign w_C[0] = 1’b0 // no carry input at first stageassign w_C[1] = w_Cg[0] |(w_Cp[0] & w_C[0]);assign w_C[2] = w_Cg[1] |(w_Cp[1] & w_C[1]);assign w_C[3] = w_Cg[2] |(w_Cp[2] & w_C[2]);assign w_C[4] = w_Cg[3] |(w_Cp[3] & w_C[3]);assign result_output = { w_C[4], w_ADD};endmoduleCarry Lookahead Adder Advantages and DisadvantagesThe advantages of CLA are:Carry lookahead adder is considered as the fastest adder when compared with other adder systems.Here, the propagation delay is minimum because the output carry bit is only based on the first carry bit which is applied at the input stage.Using the equations of carry propagate, carry generate and carry bits, CLA devices generate carry-in for every adder in a simultaneous manner.The disadvantages of CLA are:When the number of variables gets increased, the design of carry-lookahead adder becomes more complex.So, when the variables get increased and when CLA is integrated with IC, the area is required to increase.As the hardware is more, the circuitry cost becomes expensive when compared with the ripple carry adder.Please refer to this link to know more about Carry Lookahead Adder MCQsApplicationsThe carry lookahead adder applications are:Carry lookahead adders operating with high speed are employed as integrated circuits so that it is simple to integrate adder in many circuits. Also, the increase in the count of gates is even moderate when implemented for higher bits.When CLA’s are used for high-bit calculations, the device offers more speed whereas the circuit complexity also increases. Usually, these are used for 4-bit modules so that they are integrated together for high-bit computations.On a regular basis, carry-lookahead adders are used in boolean computations.What is the use of carry look-ahead adder?A CLA is a kind of adder that is mainly implemented in digital systems for performing mathematical calculations. A carry lookahead adder enhances the speed of the circuit by lowering the propagation delay which means that the time needed for carry bit

Bit is used for generating the output carry bit and this is independent of the input carry bit. The below picture shows the 4-bit carry lookahead adder architecture.4-bit Carry Lookahead Adder ArchitectureThe total number of gate levels in the circuit for carry propagation can be known from the full adder circuit. From input Cin to output Cout, two gates are required which are AND and OR gates. As w are considering a 4-bit circuit, the total number of gate levels will be 8. In the same way, for an n-bit parallel adder circuit, there is a 2n number of gate levels.For the construction of carry lookahead adder, we need two Boolean expressions which are for carry lookahead adder formula for carry propagate Cp and carry generate Cg.Cpi = Xi ꚛ YiCgi = Xi . YiWith the above expressions, the sum and carry at the output can be given as:Sumi = Cpi ꚛ CiCi+1 = Cgi + (Cpi . Ci)With the above fundamental equations, the boolean expression for carry output at every stage can be known. SoC1 = Cg0 + (Cp0 . C0)C2 = Cg1 + (Cp1 . C1) = Cg1 + (Cp1 . [Cg0 + (Cp0 . C0)])Cg1 + Cp1 . Cg0 + Cp1 . Cp0 . C0C3 = Cg2 + (Cp2 . C2)Cg2 + (Cp2 . [Cg1 + Cp1 . Cg0 + Cp1 . Cp0 . C0])C4 = Cg3 + (Cp3 . C3)Cg3 + (Cp3 . Cg2 + (Cp2 . [Cg1 + Cp1 . Cg0 + Cp1 . Cp0 . C0])As per the above equations, the carry bit of any stage is based on:Bits those are added in preceding stage and the carry bit that was provided in the initial stage.Based on the C0, C1, C2, and C3 equations, the carry lookahead adder truth table is represented as follows:XYCiCi+1Condition0000Carry generate will not be there001001000111Carry propagate will not be there100010111101Carry generate1111Also, the equations are applied using AND and OR gates which gives the carry lookahead adder circuit diagram.Carry Lookahead Adder Circuit DiagramCarry Lookahead Adder ICsThe CLA’s are combined with many ICs in multiple bit configurations. There exist various individual carry